The present invention relates generally to data processing and communication systems, and, more specifically, to determining zone statistics of a bit stream in order to recover clock and data signals.
In a data transmission and communication system, a bit stream is transmitted from a transmitter module to a receiver module through a transmission channel. At the receiver module, various clock and data recovery techniques are applied to recover data from the received bit stream. The bit stream may include a set of continuous string of binary zeroes or ones. This continuous string of binary zeroes or ones is referred to as a zone. In order to recover data from the received bit stream, the zone statistics, for example, count of zones, length of each zone, center bit position of each zone, and so forth must be determined.
Zone statistics are calculated for numerous other applications, for example, data compression techniques such as run length encoding. Run length encoding entails replacing runs or a series of consecutive occurrences of a digit or a character in a data file with code words. Each codeword indicates the number of times a digit or character is repeated. Thus, a codeword requires less storage space, thus, compressing the data file. Additionally, digitized signals have runs of a binary value (binary zero or one), indicating that the signal is not transitioning. Thus, the concept of run-length encoding may be used for compressing a bit stream. In order to encode the bit stream using run-length encoding, the encoder searches the bit stream for a beginning of an occurrence of a binary value, for example binary zero. When a zero is detected in the bit stream, the encoder initiates a counter and counts the number of times the zero occurs before a binary one is reached. Then a codeword is formed that indicates the run-length of the zone of zeroes. Thus, zone statistics (zone length) are determined for replacing the run of zeroes with a code word.
Serial data transmission systems also involve manipulation of bit streams that have runs of binary ones or zeroes. As a result, such systems require calculation of zone statistics. Typically, in a serial data transmission system, data is transmitted serially over the transmission channel without an accompanying clock signal. The receiver module receives the serial data stream, recovers the data, and performs a serial-to-parallel conversion. The serial-to-parallel conversion results in parallel data streams that enable the receiver module to operate at lower frequencies than the serial data rate.
During serial data transmission, the transmitter module converts the parallel data into serial data by time-division multiplexing the data bits. Each data bit sent over the transmission channel is represented as a pulse of a predetermined time period of high or low voltage level. The switching between the high and low voltage levels occurs in synchronization with a clock signal local to the transmitter module. However, due to scarcity of resources, the clock signal is not transmitted to the receiver module. Thus, in order to recover data from the serial data stream, the receiver module detects bit boundaries using clock and data recovery schemes such as phase adjustment (phase alignment) or phase picking. In the phase adjustment (phase alignment) scheme, a phase locked loop (PLL) is used to adjust the sampling instant to a signal eye center of the received signal. This method of data recovery entails the usage of a digital phase detector, which calculates a phase angle between an input signal and the clock signal.
In the phase picking scheme, the serial data stream is sampled at a frequency higher than the frequency of the transmitter module clock signal. Alternatively, the phase picking clock and data recovery schemes can be applied by oversampling the bit stream using multiple phases of a reference clock signal that is local to the receiver module.
Referring now to FIG. 1, a timing diagram 100 depicting oversampling of an input bit stream is shown. The timing diagram 100 includes waveforms corresponding to an input bit stream 102 as well as waveforms 104a-104d, and an indication of accumulated phase transitions 106.
The input bit stream 102 includes received data bits Rbit0-Rbit6. At the receiver unequal lengths of data bits are received due to the non-ideal nature of the transmitter module and the transmission channel. Some of the received data bits may become either prolonged or shortened as compared to an ideal bit width. Thus, the input bit stream 102 is oversampled using the phases of a reference clock signal with phases 108a-108h to obtain multiple data samples of each data bit of the input bit stream 102. The accumulated phase transitions 106 shows that there are bit transitions at phases 108a, 108d, 108g and 108h. 
The received data bit Rbit5, which corresponds to waveform 104b, is a shortened bit since it spans only 2 phases, i.e. phases 108b and 108c (an 8 phase span is ideal). Further, the received data bit Rbit6, which corresponds to waveform 104d is an elongated bit since it spans eleven phases. Additionally, it may be observed that the received data bit Rbit2, which corresponds to waveform 104a is of normal length since it spans 8 phases. The accumulated phase transitions 106 also shows that the phases 108b and 108c, and the phases 108e and 108f do not include a transition in any of the waveforms that represent the received data bits.
Referring now to FIG. 2, a data sample matrix 200 illustrating a transition vector corresponding to the oversampled input bit stream is shown. The data sample matrix 200 includes columns that correspond to phases 0 to 7, and rows that correspond to bits 0-9 of the input bit stream 102. There is also a row 204d that corresponds to a transition vector. In the data sample matrix 200, phases 0-7 correspond to the phases 108a-108h of FIG. 1. For example, phase 108a (FIG. 1) corresponds to phase 0 in the data sample matrix 200, and so forth. Further, a binary value 0 is assigned to the bit positions that correspond to the non-transitioning phases.
Clock and data corresponding to a non-transitioning phase, which is also referred as a center phase, are recovered by the receiver module. That is, a center phase is a non-transitioning phase for which clock and data are recovered from the received bit stream. The transition vector may include a set of continuous strings of binary zeroes or ones referred as zones. To identify the center phase, zone statistics such as count of zones, length of a zone, and center bit position of a zone of all zones existing in the transition vector must be calculated. Conventionally, zone statistics are calculated using sequential and combinatorial circuits. A sequential circuit that includes a set of flip-flops, a XOR gate, and a counter connected in series is used for zone statistics calculation (explained in conjunction with FIG. 3). Alternatively, a combinatorial circuit that includes a multiplexer with 2n unique combinations is used for zone statistics calculation.
Referring now to FIG. 3, a block diagram illustrating a conventional sequential circuit 300 for zone statistics calculation is shown. The sequential circuit 300 includes flip-flops 302a and 302b, a XOR gate 304, and a counter 306. A clock input signal (CLK) is provided to the flip-flops 302a and 302b, and the counter 306. The flip-flops 302a and 302b, the XOR gate 304, and the counter 306 are connected in series. An input bit stream is provided to an input of the flip-flop 302a. The output of the flip-flop 302a is provided to the flip-flop 302b and the XOR gate 304. The output of the flip-flop 302b is provided to the XOR gate 304, and the output of the XOR gate 304 is provided to the counter 306.
The counter 306 calculates and outputs the length of each zone of the input bit stream. For example, assuming the input bit stream to be ‘10011000’ which is provided serially to the flip-flop 302a, then the flip-flop 302a serially provides these bits to the XOR gate 304 and flip-flop 302b. The flip-flop 302b adds a delay in each bit that is twice the delay added by the flip-flop 302a. Thus, the XOR gate 304 compares a bit of the bit stream with the previous bit of the bit stream and therefore, detects the transitions in the bit stream. For each transition, the XOR gate 304 outputs a logic high signal. Once, a first logic high signal is received at the counter 306 it starts counting. The counter 306 stops counting when it receives a second logic high signal from the XOR gate 304. Referring to the example above, for the bits corresponding to the first and second positions, i.e., ‘10’, the XOR gate 304 outputs ‘1’, which causes the counter 306 to start counting. For the bits corresponding to the third and fourth positions, i.e., ‘01’, a second logic high signal is generated by the XOR gate 304 and is detected as a stop of the zone by the counter 306. The length between two subsequent logic high signals corresponds to the length of the zone.
The zone statistics calculation technique outlined above has several drawbacks. Since, each stage of data processing (including transition detection by the XOR gate 304) requires at least one clock cycle then the total number of clock cycles required for statistics calculation is equivalent to the number of bits in the bit stream. This makes the process of statistics calculation data dependent. Consequently, the time required for statistics calculation is increased for long bit streams. Further, the zones and their statistics are identified sequentially, which increases processing time and latency.
As known in the art, the clock and data recovery based receivers include an equalizer and an automatic gain control unit (AGC). Typically, in clock and data recovery systems, a feedback loop provides a feedback signal to the equalizer and the AGC from the clock and data recovery unit for efficient gain control. Therefore, in a scenario when the conventional sequential circuit 300 is used for clock and data recovery and zone statistics calculation, the delays due to the sequential operation increase, which results in delaying the operation of the feedback loop, which consequently increases the delay in any corrective action to be taken by the feedback loop. Thus, the overall latency is increased considerably. Such an increase in latency leads to a substantial increase in the Bit Error Rate (BER) at the receiver. Also, with increases in increase in the latency, the receiver's ability to adapt to channel conditions decreases.
Many high speed serial interfaces, such as MIPI-MPHY, USB 3.0, SATA, and PCI Express, perform error and data correction. These high speed serial interfaces provide Acknowledgement/Negative Acknowledgements (ACKS/NACKS) to the transmitters to provide feedback based on accurate or inaccurate data reception. Thus, any latency at the receiver leads to a decrease in the overall throughput of the high speed serial interfaces.
Another conventional method used to calculate the zone statistics of a bit stream is with a combinatorial circuit, such as a multiplexer. For example, for a bit stream including eight bits, a multiplexer with 28=256 input lines and eight select lines, and one output line is used. Zone statistics, such as a count of one or more zones, a center bit position of each zone, and a length of each zone, corresponding to the eight bits are calculated and stored using the 256 unique combinations that are possible for the eight bits. Thereafter, the input lines are loaded with the 256 calculated combinations and the eight bits of the input bit stream are provided on the eight select lines. This leads to the selection of one input line that is identical to the input bit stream. The unique combination on the input line is transmitted to the output line. A comparator compares the output on the output line with stored combinations. When a match is obtained, the comparator provides the zone statistics corresponding to that combination. It is evident that for designing a zone statistics calculator for an n bit stream, zone statistics corresponding to the 2n unique combinations need to be calculated and stored in a look-up table. An increase in the number of bits in the bit stream increases exponentially the number of unique combinations, making this implementation impractical. Further, the logic depth levels required to implement the above logic increases with an increase in data bits in the bit stream.
It would be desirable to have a method and system for calculating zone statistics of a bit stream that has low latency, and performs zone statistics calculation efficiently without too many clock cycles. Additionally, the system and method should enable zone statistics calculation using less logic depth levels.